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Synopsys, Inc. - EDA Software -
Category Directory
(650)
584-5000
700 East Middlefield Road
Mountain View, CA 94043
www.synopsys.com
Sales
$1.2
billion
Business Description
Synopsys, Inc. (Synopsys) is the world leader in electronic design
automation (EDA) software used to design complex integrated circuits (ICs)
and systems-on-chips (SoCs) in the global semiconductor and electronics
industries. Our software and intellectual property products and design
services provide a complete IC design and verification solution from
original concept to the actual chip, enabling our customers to bring
advanced products to market quickly.
We
provide products and services that help our customers meet the challenges of
designing leading-edge ICs. As a result of our mid-2002 acquisition of Avant!
Corporation (Avant!), we now offer a comprehensive suite of system design,
logic design, functional verification, physical design and physical
verification products. Our March 2003 acquisition of Numerical Technologies,
Inc. (Numerical) expanded our offerings of manufacturing technologies and
products geared towards small geometry designs. We also sell the broadest
array of pre-verified intellectual property (IP) components of any company
in the EDA industry. Finally, we offer a full range of professional
services, including turnkey design services, design assistance and
methodology consulting.
We
operate in a single segment and are currently organized into four primary
groups: Implementation, Verification, Solutions and New Ventures.
• Implementation Group: develops and markets the products included in the
Galaxy Design Platform and related products.
• Verification Group: develops and markets the products included in the
Discovery Verification Platform and related products.
• Solutions Group: develops and markets our DesignWare® library of
pre-designed IP blocks for chip designers and provides turnkey IC design and
verification services.
• New Ventures Group: focuses on our Design for Manufacturing initiatives
and analog/mixed-signal design and verification products.
Our other groups include Worldwide Sales, Worldwide Application Services,
Finance, Human Resources and Facilities, and Chief Technology Office.
Products and Services
Our products and services focus on the principal needs of semiconductor
designers and, at a business level, are divided into the four groups
specified above. We provide financial information regarding our products and
services under Part II, Item 7, Management’s Discussion and Analysis of
Financial Condition and Results of Operations—Results of
Operations—Revenue—Product Groups.
Implementation Group
Galaxy Design Platform. In February 2003, we announced the combination of
many of our leading IC design products into a single, unified platform
called the Galaxy™ Design Platform. Galaxy includes the following products:
• Design Compiler® is our market-leading logic synthesis tool used by a
broad range of companies engaged in the design of ICs to optimize their
designs for performance and area.
• Physical Compiler® is our physical synthesis product which unites logic
synthesis and placement functionality and addresses critical timing problems
encountered in designing advanced ICs and SoCs.
• Module Compiler™ allows designers to reuse their datapath structures to
obtain the best implementation for their designs.
• Power Compiler™ helps designers manage and verify power consumption at
different levels of the design process.
• DFT Compiler™ inserts functional and test logic required to enable
efficient, high-coverage testing of the chip after manufacturing.
• Jupiter XT™ is our hierarchical design planning tool that allows designers
to quickly partition their chip design into the best physical hierarchy to
optimize logic synthesis and physical implementation.
• Apollo™ is our basic physical design tool used for the placement and
routing of a chip.
• Astro™ is our advanced physical design system for optimization, placement
and routing while concurrently accounting for physical effects.
• PrimeTime®/PrimeTime SI are timing analysis products that measure and
analyze the speed at which a design will operate when it is fabricated.
PrimeTime SI analyzes the effect of cross-talk on timing, an increasingly
important issue at chip geometries below 180 nanometers.
• Star-RCXT™ is our industry-leading extraction solution for analyzing IC
layout data and determining key electrical characteristics of a chip, such
as capacitance and resistance.
• Hercules™ is our physical verification product family that performs
design-rule checking, electrical rule checking, and layout versus schematic
verification.
• Milkyway™ Database is a common design data repository which enables better
interoperability among implementation and analysis tools. Storing design
data in this single database with rapid read/write access can reduce data
translation times between tools and inconsistent interpretations of diverse
data. We opened this database to our customers and other EDA vendors in
February 2003 to reduce integration costs for our customers and advance tool
interoperability in the industry.
With the Galaxy Design Platform, our goal is to provide our customers a
single, integrated IC design platform based on leading individual products
which incorporates common libraries and consistent timing, delay calculation
and constraints throughout the design process using our open Milkyway
database, and yet allows designers the flexibility to integrate internally
developed and third-party tools. With this advanced functionality,
common foundation and flexibility, our Galaxy Design Platform should help
reduce design times, decrease integration costs and minimize the risks
inherent in advanced, complex IC designs.
Verification Group
Discovery Verification Platform. Also during fiscal 2003, we introduced our
Discovery™ Verification Platform. The Discovery Platform combines many of
our verification and nanometer level analysis tools in a unified environment
to provide high performance and efficient interaction among these
technologies. The Discovery Verification Platform includes the following
products:
• VCS® is our high performance software simulator that serves as the basic
engine of the Discovery Verification Platform and is often used in
simulation “farms” consisting of hundreds or thousands of computers. VCS
includes technologies that support model development, testbench creation,
coverage feedback and debugging techniques.
• System Studio is a verification environment which focuses on the
interaction between software and hardware and permits designers to model
various alternatives for their chips at a system level.
• LEDA is our programmable coding and design guideline checker that enhance
a designer’s ability to check a design for synthesizability, simulatability,
testability and reusability.
• Vera® automates the creation of “testbenches,” or custom models that
provide simulation inputs and respond to simulated outputs from the design
during verification. Automating this process significantly reduces overall
design and verification time. Vera is integrated with our other simulation
products to provide increased productivity benefits.
• Formality® is our formal verification solution that compares two versions
of a design to determine if they are equivalent. The use of formal
verification reduces the need to perform simulation, which is substantially
more time-consuming, thus potentially saving a significant amount of time in
the overall design process.
• Magellan™ combines functional and formal verification technologies to
allow engineers to find deep, corner-case software defects, or “bugs,”
quickly during verification.
• NanoSim® is our advanced, transistor level circuit simulation and analysis
product for digital, analog and mixed signal verification that offers
circuit simulation, timing and power analysis in a single tool. NanoSim is a
key component of Discovery AMS.
• HSPICE® offers high-accuracy, transistor-level circuit simulation enabling
designers to better predict the timing, power consumption and functionality
of their designs.
The Discovery Verification Platform also includes our Discovery AMS
platform, a subset of the above technologies tuned to perform verification
on analog and mixed analog-and-digital designs, and supports the latest
Accellera SystemVerilog language standard, Verilog, VHDL, mixed-HDL, SystemC,
and for analog mixed-signal based methodologies, Verilog-AMS and SPICE.
The increasing size and complexity of today’s ICs and SoCs have vastly
increased the time and effort required to verify chip designs, with test
creation and verification now consuming up to 70% of the total design time
for a given IC. Our Discovery Platform combines our simulation and
verification products and design-for-verification methodologies, and
provides a consistent control environment to significantly improve the
speed, breadth and accuracy of our customers’ verification efforts on
complex chip designs, increasing their productivity and helping them deliver
their products to market faster.
Solutions
Synopsys’ Solutions Group includes our portfolio of IP products and
components and our Consulting Services Group.
Intellectual Property Products. As IC designs continue to grow in size,
reusing proven design blocks is an increasingly important way to reduce
overall design cost and cycle time. Enabling reuse of IP requires a
significant methodology shift from traditional IC design. In the past,
designs were intimately tied to a particular semiconductor process
technology or design methodology, making reuse of design blocks from one
chip design to the next both difficult and costly. More recently, IC
companies have been able to increasingly reuse pre-designed and verified IP
components, particularly those that implement basic or standardized
functions. The ability to reuse such IP allows IC companies to focus their
design teams on designing the chip features that will give its products a
competitive advantage. Using pre-designed IP can also reduce a chip
designer’s verification risk by ensuring that the “designed in” portions of
the chip are “pre-verified” and thus high quality. Because of the increasing
importance of pre-designed IP, and in order to minimize the risk and effort
in acquiring IP from a myriad of smaller suppliers, IC designers are
beginning to consolidate their IP purchases from fewer vendors who can
provide a reliable, comprehensive portfolio of proven IP.
Our IP products include:
• DesignWare Foundation Library is an extensive library of basic chip
elements (for example, adders and multipliers) which Design Compiler uses in
logic synthesis.
• DesignWare Verification Library is our library of popular chip function
models used during the verification process of chip design.
• DesignWare Cores are pre-designed and pre-verified design blocks that
implement many of the most important industry standards, including USB (1.1,
2.0 and On-The-Go), PCI (PCI, PCI-X and PCI Express), Ethernet and JPEG.
Finally, Synopsys’ Star IP program permits DesignWare library users to gain
access to popular microprocessor cores from leading semiconductor and IP
companies. We have worked with these companies to improve the reusability of
these microprocessor cores as well as to integrate them with other
DesignWare microprocessor subsystems. The program includes cores from
companies like MIPS, NEC and Infineon, and in 2003 we added a PowerPC
microprocessor from IBM.
Professional Services. We provide a comprehensive portfolio of consulting
services covering all critical phases of the SoC development process, as
well as systems development in wireless and broadband applications. We offer
customers a variety of engagement models ranging from project assistance,
which helps our customers design, verify and/or test their chips and improve
their design processes, to full turnkey development.
New Ventures
Our New Ventures Group includes a number of products and initiatives
relating to analog/mixed signal IC design and verification and design for
manufacturing.
Analog Mixed-Signal Tools. Our Cosmos™ tool is used to create analog
designs. Cosmos uses schematic-driven layout to place and route full-custom
ICs. The New Ventures Group also manages development and marketing of our
NanoSim and HSPICE tools described above under Discovery Verification
Platform.
Design for Manufacturing. With the acquisitions of Avant! and Numerical, we
offer a variety of products and technologies used at the intersection of IC
design and manufacturing which address a variety of issues, principally
those encountered using photolithography techniques to manufacture ICs when
advanced ICs have feature dimensions smaller than the wavelength of light
used to expose those dimensions during production. We address these markets
through our Design for Manufacturing initiatives, which include:
• CATS® is our mask data preparation product that takes a final IC design
and “fractures” or “breaks” it into the physical features that will be
included in the photomasks to be used in manufacturing.
• Proteus OPC™/InPhase are optical proximity correction (OPC) products which
embed and verify corrective features in an IC design and masks to improve
manufacturing results for subwavelength feature width design. OPC applies
systematic changes to mask geometries to compensate for nonlinear
distortions caused by optical diffraction and resist process effects.
• Phase Shift Masking Technologies consist of mask design techniques that
use optical interference to improve depth-of-field and resolution in
subwavelength photolithography.
• SiVL® (Silicon versus Layout) verifies the layout of a subwavelength IC
against the silicon it is intended to produce by reading in the layout and
simulating lithographic process effects, including optical, resist and etch
effects.
• Virtual Stepper is our mask qualification product that checks mask quality
and analyzes printability of mask defects, helping to separate true defects
from nuisance defects.
The
Role of EDA in the Electronics Industry
Continuing technology advances in the semiconductor industry have
dramatically increased the feature density, speed, power efficiency and
functional capacity of semiconductors (also referred to as integrated
circuits, ICs or chips).
• Since the early 1960s, steadily decreasing feature widths (the widths of
the wires imprinted on the chip that form the transistors) and other
developments have enabled IC manufacturers to approximately double every two
years the number of transistors that can be placed on a chip. As a result,
state-of-the-art ICs now hold tens of millions of transistors and have
feature widths of 130 nanometers (billionths of an inch), going to 90
nanometers and below.
• Microprocessors operating at more than 3 gigahertz, a speed unheard of
only a few years ago, are readily available today.
• Chips have become more power efficient to address demand for smaller and
more powerful handheld devices such as cell phones and personal digital
assistants.
• Increasingly, single SoCs can handle functions formerly performed by
multiple ICs attached to a printed circuit board.
Combined, these advances in semiconductor technology have driven development
of lower cost, higher performance computers, wireless communications
networks, cell phones, hand-held personal devices, Internet routers and a
wealth of other electronic devices. Each advance, however, has introduced
new challenges for all participants in semiconductor production, including
designers, manufacturers, equipment manufacturers and EDA software
suppliers.
The IC Design Process
EDA software is central to the IC design process, as it enables designers
to:
• Address ever-increasing complexity by moving to less detailed,
higher-level design representations of the chip’s intended functionality;
• Translate these high-level representations automatically into successively
more detailed forms, from symbolic, front-end system and logic designs to
geometric, back-end physical layout designs; and
• Verify at each stage in the design process that the chip’s design is sound
and that the chip when manufactured will function as originally intended.
In simplified form, IC design consists of system design, logic design,
functional verification, physical design and physical verification.
System Design. In system design, the designer describes the chip’s desired
functions in very basic terms using a specialized high-level computer
language, typically Verilog or VHDL. This phase yields a relatively
high-level, “register transfer level” (RTL) description of the chip. System
design is an early stage market segment for EDA companies, as most EDA
products have focused to date on logic design, functional verification and
physical design and verification.
Logic Design. Logic design, or “synthesis,” programs convert the RTL code
into a logical diagram of the chip, and produce a data file known as a “net
list” describing the various groups of transistors, or “gates,” to be built
on the chip. Related programs insert into the design the additional
circuitry that will be needed to test the chip after manufacture.
In a growing number of designs, logic synthesis is performed together with a
portion of physical design. This combined process, known as “physical
synthesis,” produces a data file describing the chip plus a portion of the
chip’s physical layout. Also, in a growing number of SoCs, designers are
increasingly performing “design planning” in which the designer determines
the location of the major functional “blocks” on the SoC prior to logic
synthesis.
Functional Verification. Before and after logic design, the designer uses
testbench automation and other verification tools to simulate large sets of
inputs that a given IC design might confront in real-life operation. By
running these extensive tests, the designer can verify that the design will
function as intended.
Physical Design. In the physical design stage, the designer plans the
physical location of all of the transistors and each of the wires connecting
them with a “place and route” tool. The designer first determines the
location on the chip die for each block of the chip, as well as the location
for each transistor within each block, a process known as “placement.” Then
the designer adds the connections between the transistors, a process known
as “routing.” The output of place and route programs is one or more data
files that can be read by physical verification programs (as described
below) or by the equipment used to manufacture the chip.
Physical Verification. Before sending the chip design files to a
manufacturer for fabrication, the designer must perform a series of further
verification steps, confirming again that the chip will still operate at the
desired speed and checking to make sure that the final design complies with
the specific requirements of the fabrication facility that will manufacture
the chip. The designer may need to add features to the design to ensure that
the chip can be manufactured successfully. The completion of this final
phase is called “tapeout.”
In actual chip design, each of these steps has a number of additional
elements, and designers often undertake the various design and verification
steps in a different order than described above, and repeat one or more
steps multiple times. Further, several of the steps, especially logic design
and physical design, are becoming more integrated with each other. If at any
stage of the process the designer determines the chip design will not
perform as intended, the designer must go back one or more steps and correct
the problem, then continue through subsequent steps. Recreating a chip’s
logic design, devising and performing simulation over again, and other
iterations all take time. Each such iteration adds significant costs, and
makes it more difficult for the designer to meet time-to-market goals.
Competition
The EDA industry is highly competitive. We compete against other EDA vendors
and against our customers’ own design tools and internal design
capabilities. In general, we compete on product quality and features,
post-sale support, interoperability with other vendors’ products, price,
payment terms and, as discussed below, the ability to offer a complete
design flow.
Our competitors include companies that offer a broad range of products and
services, such as Cadence Design Systems, Inc. (Cadence) and Mentor Graphics
Corporation, and companies that offer products focused on a discrete phase
or phases of the integrated circuit design process. During the recent
semiconductor downturn, we have increasingly competed on the basis of
payment terms and price. During fiscal 2003, we increasingly agreed to
extended payment terms on our TSLs, negatively affecting our deferred
revenue and cash flow from operations. In addition, in certain situations
our competitors offer aggressive discounts on their products. As a result,
average prices may fall, and we may lose potential business where we believe
a given discount is not in our best interests.
Increasingly, EDA companies compete on the basis of design flows involving
integrated logic and physical design products rather than on the basis of
individual point tools performing a discrete phase of the design process.
The need to offer an integrated design flow will become increasingly
important as ICs grow more complex. While we have introduced design and
verification platforms that integrate many of the products required to
design an IC into a unified flow, we face significant competition from
companies that also offer their own integrated design flows, such as Cadence
and Magma Design Automation, Inc. To be successful in the future, we believe
we must further integrate our design and verification products, which will
continue to require significant engineering and development work. There can
be no guarantee that we will be able to offer a competitive complete design
flow to customers. If customers fail to adopt our design and verification
platforms or if we are unable to develop new discrete design tools or
enhance existing ones to add increased functionality or performance, our
financial condition and results of operations will be materially and
adversely affected.
Ticker
SNPS
EDA
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